The present invention is related to a semiconductor device and a method for manufacturing the semiconductor device. More specifically, the present invention is directed to an LD (Lateral Double Diffused) MOS (Metal-Oxide Semiconductor) transistor technique functioning as a high voltage element which is utilized as, for instance, a liquid crystal driving IC.
In this case, an LDMOS transistor structure implies such a transistor structure that impurities having different conductive types are diffused with respect to a region formed on the side of a surface of a semiconductor substrate so as to form new regions, and a difference between diffusions of these regions along a lateral direction is utilized as an effective channel length. Since a short channel is formed, the resulting transistor structure may constitute such an element suitably having a lower ON-resistance value.
FIG. 9 is a sectional diagram for explaining a conventional LDMOS transistor, as one example thereof, for representing an N-channel type LDMOS transistor structure. It should be noted that while a description as to a P-channel type LDMOS transistor structure is omitted, as is well known in this field, this P-channel type LDMOS transistor owns a similar structure of the N-channel type LDMOS transistor except for the conductive type thereof.
In FIG. 9, reference numeral 51 shows one conductive type semiconductor substrate, for example, a P type semiconductor substrate (P-Sub), and reference numeral 52 represents an N type well region. In this N type well region (N well) 52, a P type body region (PB) 53 is formed, whereas an N type (N+) region 54 is formed in the above-explained N type well region 53, and another N type (N+) region 55 is formed in the N type well region 52. Also, a gate electrode 58 is formed on a surface of the semiconductor substrate in such a manner that this gate electrode 58 is bridged between a first gate insulating film 56 and a second gate insulating film 57, the film thickness of which is thinner than that of the first gate insulating film 56. A channel region 59 is formed in a surface region of the P type body region 53 located just under this gate electrode 58.
Then, the above-explained N+ type region 54 is used as a source region, the N+ type region 55 is used as a drain region, and the N type well region 52 is used as a drift region. Also, reference numeral 60 shows a device separation film, symbol “S” denotes a source electrode, symbol “G” indicates a gate electrode, and symbol “D” represents a drain electrode. Reference numeral 61 shows a P type (P+) region which is employed so as to secure a potential of the P type body region 53. Also, reference numeral 62 shows an interlayer insulating film.
In the above-explained LDMOS transistor, since the N type well region 52 is formed in the diffusion manner, concentration at the surface of the N type well region 52 is increased, so that a current can easily flow on the surface of the N type well region 52, and also, this LDMOS transistor can be operated under high voltages, namely can have a high-voltage-withstanding characteristic.
In the above-described LDMOS transistor, the simulation result could reveal such a fact that local current crowding (namely, region “A” shown in FIG. 9) may occur between an edge portion of the P type body region 53 and an edge portion of the first gate insulating film 56, and thus, a current can very hardly flow between the source of this LDMOS transistor and the drain thereof.
As a consequence, in particular, when the drain voltage is low, there is a lack of drive capability of the LDMOS transistor, so that this LDMOS transistor can be hardly turned ON.
The occurrence cause of this local current crowding is given by such a fact that equipotential lines are crowded in such a space which is surrounded by an edge portion (wall) of the above-explained first gate insulating film 56 and an edge portion (wall) of the P type body region 53. More precisely speaking, while the equipotential lines may be distributed by widening the space which is surrounded by the edge portion (wall) of the first gate insulating film 56 and the edge portion (wall) of the P type body region 53, this measure may disturb, or impede that the LDMOS transistor is manufactured in very fine manners.